SystemC와 systemverilog의 OOP를 이용한 통합검증환경 설계 = Design of co-vertification environment using OOP of systemC and systemverilogy

다국어 초록 (Multilingual Abstract)

Currently, system-level design and functional verification methodology based on high-level abstraction becomes more important to increase the productivity of a SoC(system on a chip) design. The flow of a universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In the developing process of a hardware component of target system, the design phase has been regarded as a phase consuming lots of time and cost. However, the verification phase in which functionality of the designed component is verified has recently been considered as a much important phase. The typical functional verification of hardware mainly uses BFM of the design because most IPs designed for SoC are connected to a bus and controlled through the bus. The functional interaction between hardware part and software part of a design is inspected by co-verification.
Most of previous research for co-verification have used IPC with semaphore, pipe or socket for communication between C code and HDL module. In this case, user-defined system functions are added to HDL simulator through Verilog PLI in order for hardware module to use IPC, and moreover system functions of device driver or kernel are called from inside of added system functions.
In this paper, verification environments based-on SystemVerilog and SystemC, one is native-code co-verification environment which makes prompt functional verification possible and another is SystemVerilog layered testbench which makes clock-level verification possible, are implemented. In native-code co-verification, hardware and software parts of SoC are respectively designed with SystemVerilog and SystemC after hardware/software partitioning using SystemC, then the functional interaction between hardware and software parts is carried out as one simulation process. SystemVerilog layered testbench is a verification environment including corner case test of DUT through the randomly generated testvector. We adopt SystemC to design a component of verification environment which has multiple inheritance, and we combine SystemC design unit with the SystemVerilog layered testbench using SystemVerilog DPI and ModelSim macro. SystemVerilog DPI provides a way to interface with any other foreign language. Functions and tasks registered to shared library using DPI can be called out like native ones. ModelSim recently supports SystemC simulation with built-in compiler for SystemC design unit. In order to simulate SystemC design unit with ModelSim, the SystemC design unit should be modified using some macros provided by ModelSim.
As multiple inheritance is useful for creating class types that combine the properties of two or more class types, the design of verification environment adopting SystemC in this paper can increase the code reusability.

목차 (Table of Contents)

• I. 서 론 1
• 1.1 연구 배경 1
• 1.2 연구 목적 및 내용 4
• II. 시스템집적반도체 설계 방법론 7
• 2.1 시스템 수준 설계 방법론 10
• 2.1.1 시스템 수준 설계 언어, SystemC 12
• 2.1.2 SystemC 설계 방법론 17
• 2.2 하드웨어 설계 방법론 22
• 2.2.1 설계 명세 23
• 2.2.2 설계 분할 23
• 2.2.3 시스템 설계 24
• 2.2.4 검증 27
• 2.2.5 시스템 통합 및 테스트 28
• 2.3 소프트웨어 설계 방법론 29
• III. 하드웨어/소프트웨어 통합검증환경 32
• 3.1 테스트벤치 기반의 검증환경 32
• 3.2 SystemVerilog 기반의 검증환경 34
• 3.2.1 SystemVerilog 34
• 3.2.2 SystemVerilog 기반의 계층적 구조 테스트벤치 39
• 3.3 통합시뮬레이션 환경 42
• 3.4 통합에뮬레이션 환경 48
• 3.5 소켓 IPC 기반의 통합검증환경 51
• IV. OOP 기반의 통합검증환경 56
• 4.1 전송 수준 통합검증환경 57
• 4.1.1 SystemVerilog 모듈 설계 58
• 4.1.2 SystemC 디자인 유닛 설계 60
• 4.2 사이클 수준 통합검증환경 63
• 4.2.1 SystemC FIFO 채널을 이용한 통합검증환경 63
• 4.2.2 SystemC 구성요소를 이용한 통합검증환경 73
• V. 제안한 통합검증환경을 이용한 DUT 기능 검증 81
• 5.1 SystemVerilog DPI 기반의 전송 수준 통합검증 82
• 5.2 SystemC FIFO 채널을 이용한 사이클 수준 통합검증 84
• 5.3 SystemC 구성요소를 이용한 사이클 수준 통합검증 86
• VI. 결 론 89
• 참고문헌 91