TRENDS AND PERSPECTIVES IN INTEGRATED CIRCUITS AND SYSTEMS
저자
Courtois,Bernard (TIMA/CMP, France)
발행기관
학술지명
권호사항
발행연도
1995
작성언어
English
KDC
569.000
자료형태
학술저널
발행기관 URL
수록면
409-414(6쪽)
제공처
Electronics is expected to become the largest branch of industry around the year 2000, representing 10% of the world GNP. CAD represents just a bit more than i% and semiconductors 7% of the electronics market but they enable the $600 billion electronic systems' market. CAD Companies are evolving quickly, often growing through mergers and having to advance the state of their tools quickly in response to rapidly changing market needs. Major companies are Cadence and Mentor Graphics. Synopsys is growing rapidly in the synthesis market. ViewLogic was recently growing rapidly in the area of CAD tools for the low-end market. Low-end CAD tools for PCs are becoming more powerful, and are becoming more competitive with high-end products for workstations. At the same time; producers of high-end CAD tools are exploring strategies which will retain their competitive position despite the growing use of lower-end tools. Architecture synthesis tools are becoming increasingly important and developments in this area still benefit from research on silicon compilation, research that has been ongoing since the early 1980s. CATHEDRAL and AMICAL are representative of tools in this area. VHDL has become established as an important standard, along with VERILOG. In general, CAD tools are moving towards higher levels of description, with today's keywords including $quot;high-level$quot; design, $quot;system$quot; design, and $quot;architectural$quot; design. Several small companies are providing software which bridges between EDA tools and system tools. A global objective is to develop CAD tools capable of handling both hardware and software simultaneously (co-design), by bridging CASE and EDA tools. Productivity and innovation must be addressed by the research CAD community. Today, improvements in design productivity do not match the improvements occurring in the semiconductor technology, with the result that larger design teams are necessary for the more complex designs which can be placed on a single IC. The needs for advances in CAD tools remains large, though today's needs are different from those occurring a few years ago.
The cost of manufacturing may impose serious limits, perhaps more important than physical device limits, in the continuing progression toward ever more advanced semiconductor fabrication processes. In particular, reversing a long term trend, the cost per transistor may begin to increase in successive generations of the technology, leading to costs per IC which increase more rapidly than the increase in the performance of the IC. Even though shared be several semiconductor companies, the cost of developing and fabricating very large memories may become too great to allow overall profits from sales of these memory components. Approaches other than downscaling of devices may allow a continuation of the decrease in the size of a system with the next generation technologies. Such alternative approaches include multichip modules (MCMs) and 3D packaging.
MCMs are expected to show rapid market growth in the years to come, and 3D packaging prototypes are emerging. Problems to be solved inlcude testing issues, particularly those related to the full testing (including burn-in) of unpackaged, bare die, seeking to provide $quot;know good die$quot; for mounting on MCMs or for stacking into 3D units.
In the area of production testing, boundary scan has emerged as a standard. Current testing (in which power supply currents are monitored) has emerged as a useful approach, complementing voltage testing and providing coverage of faults not readily detected by verification of logic level signals (voltage testing). Built-in current sensors have been integrated directly within ICs, allowing localized current testing. Concurrent testing has been developed theoretically over the last 20 years, and the first commencia] products are on the way. The trend in CAD is toward designing from higher and higher levels of abstraction in order to handle the increasingly complex circuits, with consequences on design verification and production testing. Design verification using formal techniques are increasingly needed since the use of simulation as a verification tool is becoming less appropriate. However, research is still needed to apply these formal techniques to higher complexity circuits. Production level testing must also consider low level fault models, since the classes of faults which must be represented become increasingly related to low level transistor behavior as the speed of the ICs increase. The challenge for testing is to adequately model the very complex circuits being produced using low-level fault models. Lastly, the continuing decrease in dimensions of ICs and the development of packaging techniques make thermal issues more and more crucial [SZEKELY 95].
Among the trends impacting design tools are the increasing applications of BiCMOS and GaAs ICs, expected to comprise about 5% and 2%, respectively, of the market in 1995. While silicon CMOS becomes an even more dominant mainstream technology, silicon bipolar circuitry will become less important, becoming negligible around the year 2000. Due to downscaling of the semiconductor technologies and the need for low power consumption, the power supply voltage is decreasing from 5 V to 3.3 V as feature sizes decrease below 0.6 ㎛. New circuit design approaches will be needed to eliminate the decrease in speed caused by the lower voltage. 3D integration, providing multiple layers of monolithic circuitry, remains a long term perspective, while continuing increases in the number of metal layers is a short term focus. Finally, FPGAs are emerging as particularly important IC components for several applications markets. Finally, it might happen that the most important (r)evolution of microelectronics will be the move to microsystems. Those microsystems might go out from the research laboratories to industry, provided that foundries and multi-purpose CAD emerge.
Europe is benefiting from the development of several infrastructures. Several new European conferences been started over the past few years, the most important one being ED&TC. In the area of education, EUROCHIP has been an effort in terms of services provided to European universities, mostly in those countries which did not develop national initiatives in the past. This program is now finished. Recent initiative, CHIPSHOP, provides assistance to SMEs in the development and application of microelectronics. The prospects for the European industry presently appear strong. Some experts believe that Europe has the potential to become the world leader in semiconductors as smarter circuits such as ASICs, flash memory, EPROM, and related ICs become the main semiconductor circuit function. Initiatives such as JESSI are providing support in this direction. France, in particular, has been a pioneer in developing infrastructures for education and research, and with initiatives such as GRENOBLE 2000 placing SGS-Thomson and PHILIPS in a strong competitive position. A full paper on the topics addressed here is available [COURTOIS 94-2].
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