혼합형 테이타플로우 모델에 관한 분석 = An Analysis on the Hybrid Data-flow Models

다국어 초록 (Multilingual Abstract)

Technological advances over the past two decades have made it possible to manufacture powerful hardware components, in particular, processors and memory modules, efficiently and inexpensively. Exploiting the potential parallelism of large number of cooperating components for solving complex problems is still a major challenge to computer scientists.
And yet, there are physical limitations in the enhancement of speeding up the hardware components themselves, And also it is difficult to gain a significant improvement in performance in the conventional computer systems based on the Von-Neumann model of computation due to the 'Von-Neumann bottleneck'.
To construct a highly parallel MIMD computer, several important issues at both the software and hardware levels must be addressed. At the software level the main problem is programmability, which refers to the ability to describe a problem to the parallel machine in a convenient and efficient manner, independent of the machine configuration, i.e., the number of processors and the interconnection topology. At the architecture level, the two main issues that must be addressed by any successful multiprocessor are memory latency and synchronization. Memory latency is the time which elapses between issuing a memory request and receiving the corresponding response. Synchronization, which is the second fundamental issue in designing multiprocessors, is the need to enforce the ordering of instruction execution according to their data dependencies.
The principles of data-flow, proposed in the early 1970s as an alternative to the conventional Von-Neumann model of computation, explicitly address the issue of programmability as well as memory latency and synchronization. Programmability is facilitated through high-level declarative of functional languages. These obey the single-assignment principle, which states that any variable can be assigned a data value only once. Programs are compiled into data-flow graphs, which represent the data dependencies among instructions. Execution then proceeds in a data-driven manner : an instruction is ready to execute as soon as all the required operands are available, rather than being driven by a program counter. Since instruction execution is triggered by the availability of operands, the computation is capable of tolerating arbitrary memory latencies and allows data to arrive in an arbitrary order. Furthermore, synchronization is enforced at the instruction level, because every instruction waits for all its operands to be produced before executing.
The data-flow models can be classified into the following three categories according to the firing rule of computation unit : the data-driven model, the demand-driven model, and the hybrid model. The objective of this paper is to analyze the hybrid models and to discuss possible future directions for data-flow computers.

목차 (Table of Contents)

• 1. 서론
• 2. 자료구동형 (Data-Driven)모델
• 3. 요구구동형 (Demand-Driven)모델
• 4. 혼합형 (Hybrid)모델
• 4.1 자료구동형 모델과 요구구동형 모델의 결합
• 4.2 자료구동형 모델과 폰 노이만 계산 모델의 결합
• 4.3 요구구동형 모델과 폰 노이만 계산 모델의 결합
• 4.4 자료구동형, 요구구동형, 폰 노이만 계산 모델의 결합
• 5. 결론
• 참고문헌